The reference clock source situated at the top layer of a digital synchronous network generally uses a cesium atomic oscillator as a primary standard. Each transmission apparatus in the synchronous network is provided with a sync unit that generates a clock for use within the apparatus based on the clock signal distributed from the reference clock source.
A PLL (phase locked loop) frequency multiplier circuit provided in the sync unit is often required to perform frequency multiplication by a factor of one million so as to generate a frequency of several GHz from a frequency of several kHz. An attempt to construct such a circuit by use of a single stage PLL results in the frequency division ratio of the feedback clock being extremely large. This gives rise to a problem in that the frequency divider circuit becomes very large and also a problem in that a desired loop frequency band cannot be achieved due to a loop gain drop. In consideration of this, a two-stage PLL circuit is generally employed. A frequency is increased from several kHz to several MHz at the first stage, and is then increased from several MHz to several GHz at the second stage.
Such a two-stage PLL circuit generally has a configuration in which the two stages are both analog PLL circuits, or has a configuration in which the first PLL circuit is digital and the second PLL circuit is analog. Either configuration is required to have an increased accuracy in the first-stage PLL circuit in order to improve the overall accuracy. Mechanism for increasing the accuracy of the first-stage PLL circuit include a digital PLL circuit that employs a direct digital synthesizer (i.e., DDS), which is a circuit that generates an oscillating waveform having a frequency responsive to input digital data.
The digital PLL circuit includes a digital phase detector, a digital loop filter, and a DDS. The DDS generates a signal oscillating at frequency responsive to the value of an output signal of the digital loop filter, and the generated signal is supplied to the digital phase detector as a feedback clock. The digital phase detector detects a phase difference between every M-th pulse of the feedback clock and each pulse of the reference clock to produce a digital value indicative of the detected phase. The digital loop filter temporally integrates digital values indicative of phase differences. Through this integration, the digital value indicative of a phase difference at a given moment is weighted and added to the integrated value of previously detected phase differences, so that the oscillating frequency of the DDS is successively adjusted in response to the currently detected phase difference. Through this adjustment, the oscillating signal of the DDS is controlled such that every M-th pulse of the feedback clock and each pulse of the reference clock have no phase difference. As a result, the frequency ratio of the feedback clock to the reference clock is set to M to 1.
The DDS used in the above-described digital PLL circuit includes a phase accumulator, a waveform transforming unit, and a DA converter. The phase accumulator successively adds the output digital value of the digital loop filter to the current output value of the phase accumulator to produce an output. The register that stores an accumulated sum in the phase accumulator has a predetermined bit width. Upon exceeding the value that can be expressed by this bit width, the accumulated sum returns to a smaller value, which is the value obtained by subtracting the predetermined value plus one from the current accumulated sum. The waveform transforming unit is provided with a waveform table, and transforms a triangular digital signal generated through cumulative summation by the phase accumulator into a sinusoidal digital signal. The DA converter converts the sinusoidal digital signal into an analog signal. The sinusoidal analog signal is output from the DDS.
The output value of the phase accumulator of a DDS may be directly fed back into a digital phase detector for the purpose of improving the accuracy of the digital PLL circuit (see Patent Document 1, for example). In the two-stage PLL circuit in which the first-stage PLL circuit is digital and the second-stage PLL circuit is analog, however, an increase in the accuracy of the phase detector of the first-stage digital PLL circuit will not result in sufficiently high overall accuracy if the accuracy of the DA converter at the output of the DDS is low. In order to increase the overall accuracy of a two-stage PLL circuit, the accuracy of the DA converter at the output of the DDS may need to be increased. Achieving this goal, however, requires the use of a high-end expensive DA converter having a wide bit width, which results in an undesirable cost increase.    [Patent Document 1] Japanese Patent No. 4377696    [Patent Document 2] Japanese Laid-open Patent Publication No. 2001-044979    [Patent Document 3] Japanese Laid-open Patent Publication No. 2005-064896    [Patent Document 4] Japanese Laid-open Patent Publication No. 2006-333382    [Patent Document 5] Japanese Laid-open Patent Publication No. H03-021118    [Patent Document 6] Japanese National Publication of International Patent Application No. 2001-513974    [Patent Document 7] Japanese Laid-open Patent Publication No. H07-131492    [Patent Document 8] Japanese Laid-open Patent Publication No. 2002-198847    [Patent Document 9] Japanese Laid-open Patent Publication No. 2009-153009    [Patent Document 10] Japanese Laid-open Patent Publication No. H09-326999